Analog CMOS Neural Networks Based on Gilbert Multipliers with In-Circuit Learning

This paper examines analog CMOS circuit implementations of several common neural network algorithms. All circuits described perform in-circuit learning, using Gilbert multipliers as a primary circuit component. These include 3 μ m and 1.2 μ m designs for contrastive Hebbian learning, and Becker-Hinton networks (a variation of deltarule learning). In addition, unsupervised learning circuits for competitive learning are presented. I. I NTRODUCTION Much of the research performed in the field of neural networks is done using traditional serial computers which have been programmed to emulate the functions of the neural architecture being investigated. The problem with this approach is that, typically, training a network requires hundreds of iterations through the training set, which translates into thousands of updates of hundreds/thousands of weights. The individual weight updates which are performed are generally very simple. However, when taken as a whole a RISC workstation can take days or weeks to learn to solve the problem being investigated. In an attempt to reduce this problem, one can attempt to speed up this learning process by simulating the network on specialized vector processors. However, these are generally quite expensive. Since the learning algorithms used in most networks are relatively simple, with localized computations, it would seem reasonable to construct custom parallel hardware to perform the learning task. As well, since the integration density of analog components is much higher than an equivalent digital implementation, we feel that the most desirable implementation would be a fully custom analog VLSI system. In this paper we examine the hardware implementation of three neural network algorithms. All of these make extensive use of a CMOS version of a Gilbert multiplier. Analog CMOS Neural Networks Based on Gilbert Multipliers with In-Circuit Learning Dean K. McNeill, Christian R. Schneider, Howard C. Card Department of Electrical and Computer Engineering University of Manitoba Winnipeg, Manitoba, Canada R3T 5V6 II. T HE CMOS G ILBERT M ULTIPLIER The analog multiplier, used in the networks to follow, is a CMOS version of the bipolar widerange multiplier designed by B. Gilbert [1] . This is a transconductance multiplier which produces, as its output, a current based on the product of two differential input signals. This relationship is represented by equation (1) below.